Principal Physical Design Engineer

Jb details Engineering / Physical Design Mrcc, Spain, United Kingdm (Lndn), United Kingdm (Bristl), India Full-time Are yu an experienced Physical Design Engineer lking fr yur next challenge? Ain Silicn is actively building a pipeline f talented engineers fr future pprtunities, and we’d lve t hear frm skilled prfessinals wh are passinate abut Physical Design. With design centres acrss the UK, Spain, Hyderabad, and Mrcc, we ffer the flexibility t base this rle in any f ur glbal lcatins. If yu’re interested in explring future pprtunities with us, please click the link belw t apply and register yur interest. Purpse f rle Full Chip Physical Design (PD) Expert is respnsible fr handling the entire physical implementatin prcess f a cmplex System-n-Chip (SC) r ASIC, frm initial design handff (RTL r netlist) t final sign-ff fr manufacturing (GDSII). This rle demands deep expertise acrss all aspects f the physical design flw and the ability t drive technical decisins at the chip level. Respnsibilities
- Display custmer intimacy by demnstrating clear and custmer fcused cmmunicatin, issue reslutin & delivery t beynd expectatin and develping this apprach with the team.
- Taking wnership and respnsibility f the fullchip activity assigned and deliver n day-t-day tasks.
- Actively participate in scial engagements and create a culture f recgnitin t reward success and enhance cllabratin.
- Taking wnership f mentring / caching PD team wrking n blcks and training them n fullchip PnR and signff activities.
- Encuraging a culture f apprpriate delegating and knwledge sharing.
- Supprting the hiring t headcunt t address the current and future skills gaps and capability within the team by participating actively in the interviews.
- Crdinating and cmmunicating with crss functinal teams in defining Physical Design strategies/plans.
- Respnsible fr verseeing and caching Physical Design Engineering Managers in develping their direct reprts.
- Keeping up t date with relevant engineering advances in the field and ensure that Ain Silicn is kept at the frefrnt f the state-f-the-art technlgies, methdlgies and design prcesses as used in the industry.
- Crdinating representatin f Ain Silicn at universities, cnferences and trade shws, and presenting technical papers Essential Sft skills
- Experience in advanced technlgy ndes (e.g., 7nm, 5nm, 3nm).
- Strng crss-functinal cmmunicatin and leadership skills t drive chip-level clsure acrss RTL, STA, DFT, and packaging teams.
- Vast experience in laying ut multiple instantiated high perfrmance cre designs.
- Excellent custmer management skills.
- Prven track recrd f defining and cnducting Tp-level training fr the junir team members f PD team building rganically the team capability.
- Prven prblem-slving ability under pressure with fcus n quality, wnership, and timely delivery.
- Mentr and guide blck-level PD engineers n methdlgy and flw best practices.
- Review and apprve blck-level physical design deliverables befre integratin.
- Lead debug sessins and technical discussins fr clsure issues.
- Able t build trust thrugh pen and transparent cmmunicatin
- Reliable and dedicated t deliver n prmises and cmmitments
- Able t be Risk and Change alert .
- Ability t wrk under pressure with slid rganisatinal and creative prblem-slving skills
- Psitive mindset, demnstrates Ain SIlicn values and embraces and prmtes Ains culture.
- Self-rganisatin and ability t respnd t changing pririties quickly with excellent time management skills . Technical skills
- 10+ years f physical design experience with prven hands-n expertise in delivering three r mre Full-Chip Flrplanning & Integratin
- Ability t create flrplan frm the chip specificatin dcument.
- Chip-level flrplan creatin (macr placement, IO ring, blck alignment).
- Hierarchical and flat design integratin.
- Blck pin placement, channel planning, and aspect rati ptimizatin.
- Pad and IO Integratin
- Integrate pad cells, ESD structures, and IO rings int the tp-level layut.
- Ensure signal and pwer bumps align crrectly with pad lcatins and IO blcks. Pwer Planning & Distributin Pwer grid (PG) design and planning. Multi-vltage dmain and pwer gating implementatin. IR drp and electrmigratin (EM) analysis and ptimizatin. Bump Planning Define bump pitch, pattern (array, staggered, peripheral), and pwer/signal distributin. Wrk with package and pwer integrity teams t align bump lcatins with package ball-ut and PDN requirements. Clck Tree Synthesis (CTS) Design and ptimizatin f multi-level and multi-dmain clck trees. Experience in different multipint CTS techniques ( fr ex: fish bne, H-Tree) fr better Skew, latency, and jitter ptimizatin. Lw-pwer clck techniques (clck gating, mesh trees). Placement & Ruting Standard cell placement ptimizatin fr timing and cngestin. Full-chip and tp-level ruting (glbal and detailed). Crsstalk, antenna, and signal integrity issue mitigatin. Timing Clsure: Owns and manages full-chip timing budgeting acrss hierarchical blcks — defining, allcating, and validating timing cnstraints t ensure cnsistent and cnvergent timing clsure at SC level. Static Timing Analysis (STA) fr setup/hld clsure. Timing ECOs (cell sizing, buffering, re-ruting). Interface timing management between multiple design blcks. Tapeut data preparatin and dcumentatin. Physical Verificatin & Signff DRC, LVS, and ERC checks. Parasitic extractin (RCX) and crrelatin with STA. Signff fr IR/EM, nise, and reliability. Tapeut & Fundry Handff GDSII/OASIS generatin and validatin. Fundry rule cmpliance (DRC/LVS deck handling). Tapeut data preparatin and dcumentatin.
- EDA tl knwledge essential with either Synpsys (e.g., design cmpiler, ICC2,Fusin Cmpiler, ICV, Primetime ,StarRC) and / r Cadence (Genus, Innvus, Tempus, Vltus etc) flws and Mentr Calibre flws Attributes Able t build trust thrugh pen and transparent cmmunicatin.
- Reliable and dedicated t deliver n prmises and cmmitments.
- Ability t wrk under pressure with slid rganisatinal and creative prblem-slving skills.
- Psitive mindset, demnstrates Ain’s behaviurs and embraces and prmtes Sndrel culture
- Self-rganisatin and ability t respnd t changing pririties quickly with excellent time management skills.
- Team player with the ability t guide and mentr mre junir team members.
- Self-mtivated and able t wrk under wn initiative with excellent attentin t detail.
- Passinate and cmmitted t delivering a high standard f wrk.
- Resilient and always finds a way t succeed.