Principal Physical Design Engineer

Jb details Engineering / Physical Design Mrcc, India, Spain, United Kingdm (Lndn), United Kingdm (Bristl) Full-time # Principal Physical Design Engineer (Full Chip Expert) Lcatin: Glbal / Hybrid Department: Engineering Reprts t: Physical Design Functin Lead ## Jin Ain Silicn and Shape the Future f Semicnductr Innvatin At Ain Silicn, we're seeking an experienced Principal Physical Design Engineer t lead the physical implementatin f cmplex, cutting-edge SCs and ASICs. This is a senir technical leadership rle fr a recgnised Full-Chip Physical Design expert wh thrives n slving cmplex challenges, mentring engineering teams, and driving successful tape-uts n advanced technlgy ndes. Yu will take wnership f the cmplete physical design flw, frm RTL/netlist handff thrugh t final sign-ff and GDSII generatin, wrking clsely with crss-functinal teams acrss the glbe. ## What Yu'll Be Ding As a Principal Physical Design Engineer, yu will:
- Lead full-chip physical implementatin fr cmplex SC and ASIC designs.
- Define and drive chip-level physical design strategies, methdlgies and best practices.
- Crdinate clsely with RTL, STA, DFT, Packaging, Fundry and EDA partners t achieve successful design clsure.
- Mentr and cach Physical Design engineers, supprting capability develpment acrss the team.
- Review and apprve blck-level physical design deliverables befre integratin.
- Lead technical reviews, debug sessins and clsure activities.
- Supprt recruitment activities and cntribute t building a wrld-class Physical Design team.
- Represent Ain Silicn at universities, cnferences and industry events, sharing technical expertise and prmting innvatin.
- Ensure the team remains at the frefrnt f industry methdlgies, tls and advanced-nde technlgies. ## What We're Lking Fr ### Essential Experience
- 10+ years f Physical Design experience with a prven track recrd f full-chip delivery.
- Strng expertise in advanced technlgy ndes, including 7nm, 5nm and belw.
- Experience delivering multiple cmplex SC r ASIC tape-uts.
- Demnstrated leadership experience mentring and develping engineers.
- Strng custmer engagement and stakehlder management skills.
- Excellent cmmunicatin skills with the ability t influence technical directin acrss multiple teams. ### Technical Expertise Yu will bring deep expertise in: Full-Chip Flrplanning & Integratin
- Chip-level flrplanning and macr placement
- IO ring integratin
- Hierarchical and flat implementatin flws
- Pin placement, channel planning and cngestin management Pwer Planning & Package Integratin
- Pwer grid design and ptimisatin
- Multi-vltage dmains and pwer gating
- IR drp and electrmigratin analysis
- Bump planning and package c-design Clck Tree Synthesis
- Multi-dmain and multi-level CTS
- Clck mesh, H-tree and fishbne architectures
- Skew, latency and jitter ptimisatin
- Lw-pwer clcking techniques Placement, Ruting & Timing Clsure
- Full-chip placement and ruting
- Signal integrity, crsstalk and antenna reslutin
- MCMM timing analysis
- STA sign-ff and timing ECO implementatin
- Hierarchical timing budgeting and clsure Physical Verificatin & Tape-Out
- DRC, LVS and ERC sign-ff
- RC extractin and crrelatin
- Reliability and nise analysis
- GDSII/OASIS generatin and fundry handff EDA Tl Expertise Strng wrking knwledge f ne r mre industry-leading tl flws, including:
- Synpsys (ICC2, Fusin Cmpiler, PrimeTime, StarRC, ICV)
- Cadence (Innvus, Tempus, Vltus, Genus)
- Mentr Calibre ### Desirable Experience
- DFT integratin and ECO flws
- 2.5D/3D-IC and chiplet-based architectures
- Advanced packaging technlgies
- Master's r PhD in a relevant engineering discipline ## Persnal Attributes We're lking fr smene wh:
- Leads thrugh cllabratin, trust and transparency.
- Thrives in a fast-paced envirnment and enjys slving cmplex technical challenges.
- Demnstrates strng wnership and accuntability.
- Has a passin fr mentring and develping thers.
- Is adaptable, resilient and able t navigate changing pririties.
- Embdies Ain Silicn's values and cntributes psitively t ur culture. ## Why Jin Ain Silicn? At Ain Silicn, yu'll wrk alngside exceptinal engineers n sme f the industry's mst challenging semicnductr prjects. Yu'll have the pprtunity t influence technical strategy, mentr future talent, and help shape the next generatin f silicn slutins. If yu're a recgnised Full-Chip Physical Design expert ready t make a significant impact, we'd lve t hear frm yu. Apply tday and help us design the future.